1. Field of the Invention
The present invention relates to a nonvolatile semiconductor system and particularly to a flash (entire array erasure type) EEPROM circuit.
2. Description of the Related Art
In the accompanying drawings, FIG. 11 shows a flash type EEPROM circuit constructed in accordance with the prior art, which is illustrated as being of four-memory-transistor arrangement for simplicity.
As can be seen from FIG. 11, the flash type EEPROM circuit comprises four memory transistors 1-4 which have source regions connected to a common source line SL. The common source line SL is connected to N-channel and P-channel transistors 11 and 12. The gate electrode of the N-channel transistor 11 receives a read/write signal, while the gate electrode of the P-channel transistor 12 receives an erase signal through an interface circuit 88. The interface circuit 88 functions to convert a fluctuation of input voltage at Vdd-GND into a fluctuation of output voltage at Vpp-GND.
The control gate electrodes of the memory transistors 1-4 are connected to either word line WL1 or WL2, while the drain regions of the memory transistors 1-4 are connected to either bit line BL1 or BL2.
Address signals are inputted to X-decoder 92 and Y-decoder 94 through an address buffer 90. In response to this, the X-decoder 92 generates word line signals to the word lines WL1 and WL2, while the Y-decoder 94 generates Y-decoder signals, which are in turn outputted therefrom to a bit line control circuit 95 and a sense amplifier 96.
The bit line control circuit 95 is responsive to the Y-decoder signals to control the writing of data. More particularly, the bit line control circuit 95 writes data signals, inputted through the data buffer 98, in the memory transistors 1-4 at addresses represented by the Y-decoder signals. The bit line control circuit 95 also controls the erasing and reading-out at the memory transistors 1-4.
On the other hand, the sense amplifier 96 reads out data stored in the memory transistors 1-4 using the Y-decoder signals as addresses. The read data are then outputted, as data signals, from the sense amplifier 96 to any external unit through the data buffer 98.
The operation of such a prior art system will now be described with reference to FIG. 12 which illustrates the voltages at various different components.
The writing operation will first be described. In writing operation, read/write and erase signals are set at VDD level to place the transistor 11 in ON state and the transistor 12 in OFF state, respectively, as shown in FIG. 12. Thus, the common source line SL is set at GND level. When the writing operation is to be carried out for the memory transistor 1, the word and bit lines WL1 and BL1 are set at high voltage Vpp level (e.g. 12 volts), and WL2 and BL2 are set at GND level.
Under the above setting, the control gate electrode and drain region of only the memory transistor 1 are simultaneously placed at voltage of Vpp level to generate a channel current. As a result, hot electrons are generated at the drain region edge to inject electrons into the floating gate electrode. This causes the writing operation to be carried out for the memory transistor 1 so that data "0" will be stored therein. On the other hand, no channel current is generated in the other memory transistors 2-4 since the voltages at their control gate electrodes and drain regions are not simultaneously at Vpp level. Therefore, the writing operation will not be carried out for the memory transistors 2-4.
The erasing operation will be described. In the erasing operation, read/write and erase signals are set at GND level to turn the transistors 11 and 12 respectively off and on, as shown in FIG. 12. The common source line SL is thus set at Vpp level. In addition to such settings, the word lines WL1 and WL2 are set at GND level, while the bit line BL1 and BL2 are set at Open level.
Under the above setting, the source regions of the memory transistors 1-4 will be set at Vpp level while the control gate electrodes of the memory transistors will be set at GND level. Therefore, a tunnel current will be generated between the floating gate electrode and the source region in each memory transistor. As a result, electrons will be released from the floating gate electrode to the source region to perform the erasing operation.
The reading operation will be described. In the reading operation, read/write and erase signals are set at VDD level to turn the transistors 11 and 12 respectively on and off, as shown in FIG. 12. The common source line SL is thus set at GND level. When data is to be read out from the memory transistor 1, the word lines WL1 is set at VI)D level; the bit line BL1 is set at read-out level Vred which is a positive voltage (e.g. 1 volt); the word line WL2 is set at GND level; and the bit line BL2 is set at Open level.
Under the above setting, only the memory transistor 1 will have the control gate electrode of VDD level, the drain region of Vred level and the source region of GND level. When the writing operation has been carried out for the memory transistor 1, or when data "0" has been stored in the memory transistor 1, the drain current will not flow in the bit line BL1. On the contrary, when the writing operation has not been carried out for the memory transistor 1, or when data "1" has been stored in the memory transistor 1, the drain current will flow in the bit line BL1. Therefore, the stored data can be read out by detecting the drain current at the sense amplifier 96.
The prior art has such a problem as that the electrons are excessively released to make the threshold voltage of the memory transistor negative or to produce an overerasing phenomenon, in the erasing operation.
It is now assumed that the memory transistor 3 has been overerased. It is also assumed that the writing operation has stored data "0" in the memory transistor 1. If data is read out from the memory transistor 1 under such a condition, any current ought not to flow through the bit line BL1, since the data "0" has been stored in the memory transistor 1. If the memory transistor 3 has been overerased, however, the drain current will flow even though the control gate electrode is at GND level, as shown in FIG. 11. The drain current causes the sense amplifier 96 to be subjected to malfunction, leading to a wrong judgment that the data "1" has been stored in the memory transistor 1. It results in the reading operation error.
One of techniques for preventing such an overerasing is described in Japanese Patent Application Laid-Open No. Hei 1-294297. The technique detects an electric current flowing through a memory transistor during the erasing operation. If the current is detected, the transistor providing the erasing voltage is turned off to stop the erasing operation.
This technique is disadvantageous in that means for detecting the current to turn the transistor off becomes complicated to increase the circuit in scale. Further, at a time when a memory transistor is overerased, the erasing operation For the other memory transistors is also stopped. This reduces the lower limit of operation margin in the other memory transistors.
Another technique for preventing the overerasing is a technique known as a verifying operation that is described in Japanese Patent Application Laid-Open No. Hei 4-3395, for example. The verifying operation monitors the threshold voltages in all the memory transistors at all times after the erasing operation. If the threshold voltages in all the memory transistors are equal to or lower than a preselected verify voltage, it is judged that a proper erasing operation has been carried out For each of the memory transistors. At this time, the subsequent erasing operations will be stopped. On the other hand, if the threshold voltage in even only one memory transistor is higher than the verify voltage, it is judged that the erasing operation has not properly been carried out. After the erasing operation has again been performed, the verifying operation is again carried out. The verifying and erasing operations will be repeated until all the memory transistors are properly erased.
However, the verifying operation has such a problem as that the circuit is undesirably increased in scale with a complicated control. Furthermore, the verifying operation cannot prevent the overerasing for a memory transistor erasable more quickly, that is, such a memory transistor that its threshold voltage is more shifted to the negative direction in the erasing operation.